Semiconductor memory device with a plurality of column select lines and column driving method therefor

ABSTRACT

A semiconductor memory device with a plurality of column select lines and a column driving method therefore are disclosed. In a semiconductor memory device including memory blocks each having a plurality of column lines and including a column decoder for receiving a plurality of column predecoding signals and selecting the column lines, the column lines contained in each of the memory blocks are divided into a plurality of column groups. Divided column predecoding lines for selecting the column lines contained in the column groups are arranged in a corresponding memory block, and the divided column predecoding line groups adjacently extend over any one side of the corresponding memory block.

BACKGROUND OFT HE INVENTION

The present invention relates to semiconductor memory devices, and moreparticularly to a semiconductor memory device and a column drivingmethod therefor which generates a plurality of column select lines froma plurality of predecoding signals and select a column of a memory cellarray.

A typical semiconductor memory device includes a memory cell arrayconsisting of a plurality of word lines, bit lines and memory cells, andstructure for writing or reading necessary data by designating a memorycell included in such a memory cell array. As is well known to thoseskilled in the art, specific data is written into or read from aspecific memory cell by generating a plurality of decoding signalscorresponding to a row and a column using an address applied from theexterior of the chip and then appropriately arranging and driving thesedecoding signals. A peripheral circuit column decoder performs suchfunctions and receives predecoding signals generated from a predecoderand generates column select signals for connecting a bit line within theselected memory cell array to an input/output line.

FIG. 1 illustrates a conventional column decoder. Column signalsDCA3B4B, DCA3B4, DCA5B6B and DCA7B, supplied to a NOR logic circuitNOR1, consisting of PMOS transistors P1-P3 and NMOS transistors N1-N3,and to another NOR logic circuit NOR2 consisting of PMOS transistorsP4-P6 and NMOS transistors N4-N7, are used for selecting column linesdivided into a few groups from a portion of the memory cell array.Assuming that an 8 Megabit (Mb) memory cell array is split into 4 memorybanks each having 2 Mb capacity, each memory bank is split into 4 memoryblocks, and column lines of each memory block are divided into 32 groups(hereinafter referred to as "column groups"), the above-described columnpredecoding signals are used for selecting one column group by thecombination of original column predecoding signals DCA3, DCA4, DCA5,DCA6 and DCA7, which are used for selecting 128 column linescorresponding to one memory block.

NOR gates NR1-NR4 and NR5-NR8 commonly receive the signals generatedfrom the NOR logic circuits NOR1 and NOR2, respectively. The NOR gatesNR1 and NR5 commonly receive a column predecoding signal DCA0B1B2BU. TheNOR gates NR2 and NR6 commonly receive a column predecoding signalDCA0B1B2BL. The NOR gates NR3 and NR7 commonly receive a columnpredecoding signal DCA01B2BU, and the NOR gates NR4 and NR8 commonlyreceive a column predecoding signal DCA01B2BL. The symbols -U and -L areused for classifying a pair of column select signals from one memoryblock, and hereinafter they will be used for that purpose. The NOR gateNR1 generates a column select signal CSL0U via series-connectedinverters I1 and I5 and the NOR gate NR2 generates a column selectsignal CSL0L via series-connected inverters I2 and I6. The NOR gate NR3generates a column select signal CSL1U via series-connected inverters I3and I7 and the NOR gate NR4 generates a column select signal CSL1L viaseries-connected inverters I4 and I8. The NOR gate NR5 generates acolumn select signal CSL2U via series-connected inverters I9 and I13 andthe NOR gate NR6 generates a column select signal CSL2L viaseries-connected inverters I10 and I14. Similarly, the NOR gate NR7generates a column select signal CSL3U via series-connected invertersI11 and I15 and the NOR gate NR8 generates a column select signal CSL3Lvia series-connected inverters I12 and I16.

Referring to FIG. 2, the above-described column decoder is applied to aconventional semiconductor memory device. In FIG. 2, one memory bank of2 Mb memory capacity corresponding to a quarter of a memory cell arrayis shown. One memory bank is divided into 4 memory blocks MB1, MB2, MB3and MB4. One memory block consists of 128 column lines and 128 columnselect signals CSL0U, CSL0L, CSL1U, CSL1L, . . . , CSL63U and CSL63Lcorresponding thereto. One memory block is classified into 8 subblocksSB1-SB8 each having 256 word lines. The symbol A designates a strappingarea for connecting the column select signal to the column predecodingsignal.

As shown in FIG. 2, 16 column predecoding lines 6, which transmit 16column predecoding signals DCA0B1B2BU-DCA012L, extend across all memorybanks to select the column lines corresponding to the memory bank of 2Mb. This occupies a substantial peripheral circuit area. Further, sincethese lines use conductive polysilicon, the lines are lengthened, andthus, the signal transmission speed and efficiency are lowered due toline loading.

In the actual layout of the semiconductor memory device, 128 columnlines (lines to which the column select signals are buried) included inone memory block are not respectively strapped with the columnpredecoding lines (lines to which the column predecoding signals areburied). There are 4 strapping areas, and 32 column lines are strappedwith the column predecoding lines at one strapping area in order toraise the efficiency of a manufacturing process and design. In thesemiconductor memory device, such lines use conductive polysilicon andare formed at the same level as polysilicon used in the gate of atransistor. At the strapping area between the column lines and thecolumn predecoding lines, it is inevitable that signal transition speedis delayed due to the loading of the polysilicon. If the columnpredecoding lines are extended over one memory bank as shown in FIG. 2,such phenomenon becomes worse.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a semiconductormemory device with an improved layout.

It is another object of the invention to provide a semiconductor memorydevice which increases signal transmission and transition speed intransmitting a column related signal.

It is a further object of the invention to provide a column drivingmethod for achieving a noise distribution effect in transmitting acolumn related signal.

According to one aspect of the invention, in a semiconductor memorydevice including memory blocks each having a plurality of column linesand including a column decoder for receiving a plurality of columnpredecoding signals and selecting the column lines, the column linescontained in each of the memory blocks are divided into a plurality ofcolumn groups. Divided column predecoding lines for selecting the columnlines contained in the column groups are arranged in a correspondingmemory block, and the divided column predecoding line groups adjacentlyextend over any one side of the corresponding memory block.

According to another object of the invention, in a column driving methodfor a semiconductor memory device including memory blocks each having aplurality of column lines and including a column decoder for receiving aplurality of column predecoding signals and selecting the column lines,the column lines contained in each of the memory blocks are divided intoa plurality of column groups. Divided column predecoding lines forselecting the column lines contained in the column groups are arrangedin a corresponding memory block, and one column group is simultaneouslyactivated from each memory block.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a conventional column decoder used in asemiconductor memory device;

FIG. 2 illustrates a conventional column decoding construction; and

FIG. 3 illustrates a column decoding construction according to thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The capacity of a memory cell array shown in FIG. 3 is the same as thatshown in FIG. 2. That is, 4 memory blocks MB1-MB4 have the memorycapacity of 2 Mb. Each memory block is divided into 8 subblocks SB1-SB8.128 column lines are arranged in one memory block and these column linesare divided into 32 groups. Respective memory blocks MB1-MB4 arerespectively connected to corresponding column decoders DCD1-DCD4. Instrapping column select signals with column predecoding signals, eachmemory block has 4 strapping areas consisting of 32 column lines andcolumn predecoding lines. It should be noted that the construction ofFIG. 3 and that of FIG. 2 differ widely in the connected relationshipbetween the column select signals and the column predecoding signals andthe layout of lines therefor.

In the layout of column lines 11 to which the column select signalswithin each memory block are buried, the column select signals arearranged in order of CSLiU, CSLiL, CSLjU and CSLjL (where i=0+8n,j=1+8n, n=0-31) at the first memory block MB1. That is, the order is asfollows: CSL0U, CSL0L, CSL1U, CSL1L, CSL8U, CSL8L, CSL9U, CSL9L, . . . ,CSL248U, CSL248L, CSL249U, CSL249L. At the second memory block MB2, thecolumn select signals are arranged in order of CSLiU, CSLiL, CSLjU andCSLjL (where i=2+8n, j=3+8n, n=0-31). That is the order is as follows:CSL2U, CSL2L, CSL3U, CSL3L, CSL10U, CSL10L, CSL11U, CSL11L, . . . ,CSL250U, CSL250L, CSL251U, and CSL251L. At the third memory block MB3,the column select signals are arranged in order of CSLiU, CSLiL, CSLjUand CSLjL (where i=4+8n, j=5+8n, n=1-31). That is, the order is asfollows: CSL4U, CSL4L, CSL5U, CSL5L, CSL12U, CSL12L, CSL13U, CSL13L, . .. , CSL252U, CSL252L, CSL253U, and CSL253L. At the fourth memory blockMB4, the column select signals are arranged in order of CSLiU, CSLiL,CSLjU and CSLjL (where i=6+8n, j=7+8n, n=0-31). That is, the order is asfollows: CSL6U, CSL6L, CSL7U, CSL7L, CSL14U, CSL14L, CSL15U, CSL15L, . .. , CSL254U, CSL254L, CSL255U, and CSL255L. Line groups 13 (4 bits), 14(4 bits) and 15 (2 bits) in which column predecoding signals DCA34,DCA56 and DCA7 for selecting 32 column groups divided within each memoryblock extend over all 4 memory blocks. However, column decoding lines16, 17, 18 and 19 conveying column predecoding signals (combinationsignals of DCA0, DCA1, DCA2, -U and -L) for generating the column selectsignals to select 4 column lines contained in each of 32 column groupswithin each memory block extend over the core of certain of the memoryblocks. That is, at the first memory block MB1, 4 column decoding lines16 corresponding to column predecoding signals DCA0B1B2BU, DCA01B2BU,DCA0B1B2BL and DCA01B2BL are extended. At the second memory block MB2, 4column decoding lines 17 corresponding to column predecoding signalsDCA0B12BU, DCA012BU, DCA0B12BL, and DCA012BL are extended. At the thirdmemory block MB3, 4 column decoding lines 18 corresponding to columnpredecoding signals DCA0B1B2U, DCA01B2U, DCA0B1B2L and DCA01B2L areextended. At the fourth memory block MB4, 4 column decoding lines 19corresponding to column predecoding signals DCA0B12U, DCA012U, DCA0B12L,and DCA012L are extended.

In activating a column included in each memory block, the column selectsignals driving 4 column lines contained in one column line group(corresponding to one strapping area) are activated at each memory blockduring one data access cycle. That is, 4 column lines are driven at eachmemory block and 16 column lines are simultaneously driven. For example,at the first memory block MB1, the column select signals CSL0U, CSL0L,CSL1U and CSL1L, driving 4 column lines included in the first columngroup (the first strapping area), are activated. At the second memoryblock MB2, the column select signals CSL2U, CSL2L, CSL3U and CSL3L,driving 4 column lines included in the first column group (the firststrapping area), are activated. At the third memory block MB3, thecolumn select signals CSL4U, CSL4L, CSL5U and CSL5L, driving 4 columnlines included in the first column group (the first strapping area), areactivated. At the fourth memory block MB4, the column select signalsCSL6U, CSL6L, CSL7U and CSL7L, driving 4 column lines included in thefirst column group (the first strapping area), are activated. Thus,effective noise distribution can be achieved by distributing the columnlines to each memory block.

The column predecoding lines shown in FIG. 3 are strapped by 32 areasper memory block, and the same applies to FIG. 2. However, FIG. 3 showsthe shortened length of column decoding lines compared with FIG. 2 inwhich each of 16 column decoding lines extend over all 4 memory blocks.Hence, the delay of signal transmission or lowering of the signaltransition speed caused by the line loading of polysilicon and capacitycan be suppressed.

In FIG. 3, since the column predecoding lines contained in each memoryblock can be arranged at an area in which power voltage and a groundvoltage power are formed, more unused chip space than the FIG. 2 layoutis ensured. When implementing block writing in a video RAM, etc., theconstruction of FIG. 2 may create noise due to mutual capacitance sinceadjacent column lines of a few bits are driven within one memory block.In FIG. 3, since the column lines in one memory block are not adjacentto two 2 Mb memory banks, overall noise suppression occurs.

As described above, line loading from the column predecoding line to thecolumn line within the memory cell array is reduced. Therefore, thetransmission efficiency of the column select signal is improved and themargin of layout is increased. Furthermore, noise is reduced, especiallywhen block writing operations are performed.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that foregoing and other changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A semiconductor memory device comprising:a memory array including a plurality of memory blocks, each memory block including:a plurality of column lines which form a plurality of column groups, and a column decoder for receiving a plurality of column predecoding signals and selecting one of said plurality of column lines; and a plurality of divided column predecoding lines for transmitting said column predecoding signals to each of said column decoders, certain of said plurality of divided column predecoding lines extending by each of said column decoders, and other of said plurality of divided column predecoding lines extending by only one of said column decoders.
 2. The semiconductor memory device according to claim 1, wherein said plurality of divided column predecoding lines is divided into a plurality of predecoding line groups, each predecoding line group containing a sub-plurality of divided column predecoding lines which correspond to one of said memory blocks.
 3. The semiconductor memory device according to claim 2 wherein each of said column lines has a corresponding address, and wherein said column lines are arranged such that addresses of column lines in each column group of each memory block do not sequentially correspond with addresses of column lines of other column groups of the same memory block.
 4. The semiconductor memory device according to claim 3 wherein each column group contains two column lines.
 5. The semiconductor memory device according to claim 3 wherein said column lines are arranged such that one column line from each of said column groups is simultaneously activated during a column select operation.
 6. The semiconductor memory device according to claim 3 wherein said plurality of memory blocks is at least four and each of said four memory blocks contain two column lines in said column group which correspond to two sequential addresses out of eight sequential addresses from a sequential group of addresses of said memory array.
 7. The semiconductor memory device according to claim 6 wherein each of said plurality of memory blocks has a memory capacity of at least 2 Mb.
 8. A semiconductor memory device comprising:a memory array including a plurality of memory blocks, each memory block including:a plurality of column lines which form a plurality of column groups, and a column decoder for receiving a plurality of column predecoding signals and selecting one of said plurality of column lines; and a plurality of divided column predecoding lines for transmitting said column predecoding signals to each of said column decoders, certain of said plurality of divided column predecoding lines extending by each of said column decoders, and other of said plurality of divided column predecoding lines extending by only some of said column decoders.
 9. The semiconductor memory device according to claim 8, wherein said plurality of divided column predecoding lines is divided into a plurality of predecoding line groups, each predecoding line group containing a sub-plurality of divided column predecoding lines which correspond to one of said memory blocks.
 10. The semiconductor memory device according to claim 9 wherein each of said column lines has a corresonding address and wherein said column lines are arranged such that addresses of column lines in each column group of each memory block do not sequentially correspond with addresses of column lines of other column groups of the same memory block.
 11. The semiconductor memory device according to claim 10 wherein each column group contains two column lines.
 12. The semiconductor memory device according to claim 10 wherein said column lines are arranged such that one column line from each of said column groups is simultaneously activated during a column select operation.
 13. The semiconductor memory device according to claim 10 wherein said plurality of memory blocks is at least four and each of said four memory blocks contain two column lines in said column group which correspond to two sequential addresses out of eight sequential addresses from a sequential group of addresses of said memory array.
 14. The semiconductor memory device according to claim 13 wherein each of said plurality of memory blocks has a memory capacity of at least 2 Mb.
 15. A column driving method for a semiconductor memory device including a plurality of memory blocks each having a plurality of column lines and including a column decoder for receiving a plurality of column predecoding signals and selecting certain of said plurality of column lines, said method comprising the steps of:dividing said plurality of column lines contained in each of said memory blocks into a plurality of column groups; arranging a plurality of divided column predecoding lines for selecting said column lines into a plurality of predecoding line groups, each predecoding line group containing a sub-plurality of divided column predecoding lines which correspond to one of said memory blocks; and simultaneously activating one column group from each memory block.
 16. The column driving method according to claim 15 wherein the step of arranging said plurality of divided column predecoding lines includes the step of extending certain of said plurality of divided column predecoding lines by each of said column decoders, and extending other of said plurality of divided column predecoding lines by only some of said column decoders.
 17. The column driving method according to claim 15 wherein the step of dividing said plurality of column lines includes the step of dividing said column lines so that addresses in each column group of each memory block do not sequentially correspond with addresses of other column groups of the same memory block. 